In the art of digital signal processing, the use of master-slave flip-flops is well known. A series of such flip-flops may be connected together in a chain to form a shift register. Typically, the flip-flops in a shift register are all controlled by single clock, so as to synchronize the operation of the flip-flops.
At a clock signal transition, each flip-flop will latch a new data bit at its input and push the previous data bit to its output. Because of propagation delay through the flip-flop, the output signal transition typically occurs after the input data bit is latched. Thus, if the flip-flops are synchronized perfectly, the output signal of one flip-flop will be latched by the next flip-flop in the chain before the output signal of the first flip-flop changes.
However, the clock signal will not reach each flip-flop at exactly the same time due to differences in the line delay to the clock inputs of the flip-flops. If the clock signal to a flip-flop is sufficiently delayed relative to the clock signal to the previous flip-flop in the chain, then data may be incorrectly transferred between the flip-flops. As a result, the input data received by the shift register will be corrupted during the shifting process.
This so-called racing problem may be eliminated by building in additional line delays as needed between the flip-flops in the shift register. However, to properly compensate for existing line delays, the additional line delays must be specifically tailored to the design of the circuit chip. This adds significantly to the burden of designing a chip.